This invention relates to a difference voltage amplifier circuit for amplifying a differential voltage between an input signal voltage and a reference voltage.
By convention, a general parallel A/D (analog to digital) converter is provided with a plurality of differential amplifiers each composed of a bipolar transistor. This type of parallel A/D converter will be described referring to FIG. 1. In FIG. 1, reference numeral 1 designates a voltage divider composed of resistors. Positive and negative reference voltages +Vref and -Vref are applied to the terminals of the voltage divider 1. The divided voltages derived from the interconnection points of the resistors connected in series are input, as reference voltages Vref.sub.1 -Vref.sub.n, to the input terminals of the differential amplifiers 2.sub.1 -2.sub.n composed of bipolar transistors, those input terminals each being one of the input terminals of each of the differential amplifiers 2.sub.1 -2.sub.n. An input signal voltage Vin is applied to the other input terminals of the differential amplifiers 2.sub.1 -2.sub.n, where the input signal voltage Vin is compared with the reference voltages Vref.sub.1 -Vref.sub.n. The differential amplifiers 2.sub.1 -2.sub.n respectively amplify differences between the input signal voltage Vin and the reference voltages Vref.sub.1 -Vref.sub.n. The output signal voltages Vo.sub.1 -Vo.sub.n are input to an encoder 3 where these are encoded. Then, the encoded signal is applied through an output resister 4 to a buffer 5, which in turn produces digital signals D and D.
In the example mentioned above, the differential amplifiers 2.sub.1 -2.sub.n are composed of bipolar transistors, even several tens of MHz can be sampled, i.e., the circuit is operable at high speed.
With such an arrangement, the offset voltages of the differential amplifiers 2.sub.1 -2.sub.n differ depending on the magnitudes of the reference voltages Vref.sub.1, Vref.sub.2, . . . , Vref.sub.n to the differential amplifiers 2.sub.1 -2.sub.n. This fact implies that the circuit has a problem of linearity. Further, differential amplifiers using the bipolar transistors require great power dissipation.
Another known approach to solving such a problem is an A/D converter using the chopper type comparator, as shown in FIG. 2. In the chopper type comparator, the first input terminal 6 is applied with a reference voltage Vref (FIG. 3C). The second input terminal 7 is applied with an input signal voltage Vin (FIG. 3C) to be compared with the reference voltage Vref. The first and second input terminals 6 and 7 are connected to a first terminal or input electrode of a capacitor 10, through first and second switches 8 and 9. The first and second switches 8 and 9 are analog switches made of FETs (field effect transistors), for example. These switches are on-off controlled by a clock signal .phi. (FIG. 3A) and its inverted signal .phi. (FIG. 3B) The reference voltage Vref and the input signal voltage Vin are applied to the first terminal of the capacitor 10, through the first and second switches 8 and 9. A second terminal or output electrode of the capacitor 10 is connected to the input terminal of an inverting amplifier 11 composed of a MOS transistor. A third switch 12 made up of an FET analog switch, for example, which is on-off controlled by the clock signal .phi., is provided between the input and output terminals of the inverting amplifier 11. The output signal Vout (FIG. 3D) of the inverting amplifier 11 is taken out through an output terminal 13.
With such an arrangement, during the "H" level period of the clock signal .phi. (FIG. 3A), the first switch 8 and the third switch 12 are turned on, while the second switch 9 is turned off. Therefore, the input electrode of the capacitor 10 is applied with the reference voltage Vref (FIG. 3C). The input and output terminals of the inverting amplifier 11 are short-circuited so that the input voltage of the inverting amplifier 11 may be made a threshold voltage V.sub.TH of the inverting amplifier 11, i.e., an operating point voltage as a reference voltage for the circuit operation. During the "H" level period of the clock .phi. (FIG. 3B), the first and third switches 8 and 12 are turned off, while the second switch 9 is turned on. Accordingly, the input electrode of the capacitor 10 is applied with the input signal voltage Vin.
Then, the input voltage, i.e., the threshold voltage V.sub.TH, to the inverting amplifier 11 changes by a difference (Vin-Vref). A change of the input voltage is multiplied by an amplification factor of the inverting amplifier 11 and is taken out as a circuit output signal Vout (FIG. 3D) from the output terminal 13. As described above, in this comparator of FIG. 2, it is possible to obtain an output signal Vout (FIG. 3D) composed of a train of pulses in synchronism with the clock signal .phi. by setting the reference voltage Vref at a proper value with respect to the input signal voltage Vin (FIG. 3C). In this way, the above-mentioned circuit arrangement alternately repeats an autozeroed mode in which the circuit operating point is set up by shorting the input and the output of the inverting amplifier 11, and a signal amplifying mode for inputting to the inverting amplifier 11 a difference between the input signal voltage Vin and the reference voltage Vref and amplifying the same. Through this operation, an output signal voltage Vout shown in FIG. 3D is obtained.
The comparator as mentioned above has a low power dissipation since the inverting amplifier 11 is composed of the MOS transistor. However, since this chopper type of comparator operates as a sampling system, it will be understood from the sampling theory that the comparator fails to correctly sample the input signal voltage Vin when the frequency of the input signal voltage Vin is higher than 1/2 the frequency of the clock signal .phi.. To perform high speed sampling, the influence of both a stray capacitance and an ON resistance, becomes distinctive because the ON duration of the switch is short in the high speed sampling operation. The stray capacitance and the ON resistance cause a signal transfer delay, a gain loss, etc. Further, a stray capacitance, which appears between the signal input terminal and the signal output terminal, and the control terminal of the switch for receiving the clock .phi., cause a feedthrough of clock pulses into the input signal to produce whiskerlike pulses at the level-changing of the clock pulse. This pulse signal renders the output signal unstable. Following this unstable state, a relatively long time is required until the circuit operation settles down to be stable. Because of this, the high speed circuit operation is damaged from a dynamic viewpoint of the circuit, and the output signal of the circuit is set off from a static viewpoint.